EE5518代做、Python，Java编程代写

日期：2023-10-15 11:01

Lab Assignment 1

EE5518 – AY2023/2024 Sem1

Submission Deadline: 16

th October’23 11:59AM

Lab experience 1: Getting started with Cadence Virtuoso via Interconnect Modelling and Simulation.

Consider a 2-core processor with 2 dedicated GPUs and 2 DSP cores in 45nm operating at 1V and max

frequency of 200MHz. The path to each block from the RESET PIN is shown in Fig. 1 along with the

corresponding global/intermediate (solid-black/dotted-blue) interconnect lengths. The interconnects are

assumed to be drawn with minimum widths allowed by the technology node. Using an ideal voltage source

VRST and a 3kΩ resistor at the RESET PIN, reset signal is triggered at t = 0, synchronous to rising edge of

clock. The input capacitance of the reset buffer in each block is shown via the dashed arrows in Fig. 1.

GPU 1

GPU 2

DSP 1 CPU 1

VRST

2.5m m 4m m

1.5mm 1.5mm

1.5mm 1.5mm

RESET PIN

CL, GPU1 = 5fF

CL, DSP1 = 3fF CL, CPU1 = 5fF

`

`

CL, GPU2 = 5fF

` `

DSP 2 CPU 2

1m m 1m m

CL, DSP2 = 3fF CL, CPU2 = 5fF

` `

1m m 1m m

` `

`

`

RRST = 3kΩ

`

RST

CLK

t

t

at t=0,

RST is triggered

t = 0

Fig. 1: Reset interconnect path in 2-Core Processor with timing diagram

Table A: Interconnect technology data in 45-nm – intermediate and global metal

technology

parameter definition value

(intermediate wire)

value

(global wire)

physical

constants

rw

wire resistance

per unit length 1.20 Ω/μm 0.05 Ω/μm

cw

wire capacitance

per unit length 0.13 fF/μm 0.19 fF/μm

Assume that the rise and fall delay for all signals is 0 and there is no coupling capacitance between the

interconnects. It is also assumed that clock is ideal and there is no clock skew between the blocks. You

may refer to the technology parameters in Table A.

GPU 1

GPU 2

DSP 1 CPU 1

VRST

2.5m m 4m m

1.5mm 1.5mm

1.5mm 1.5mm

RESET PIN

CL, GPU1 = 5fF

CL, DSP1 = 3fF CL, CPU1 = 5fF

`

`

CL, GPU2 = 5fF

` `

DSP 2 CPU 2

1m m 1m m

CL, DSP2 = 3fF CL, CPU2 = 5fF

` `

1m m 1m m

` `

`

`

RRST = 3kΩ

`

6.5m m

6.5m m

Fig. 2: Modified reset interconnect path in 2-Core Processor for Q4. & Q5.

Q1. Draw the equivalent circuit for the described interconnect path in Fig. 1. Annotate all the R, C values

on the equivalent circuit, and estimate the propagation delay from RESET PIN to each receiver

module using Elmore delay method with π lumped RC model.

Q2. Build the schematics and testbench for the equivalent circuit in Q1. Simulate your testbench and verify

the hand calculation results in Q1.

Q3. Assuming that Recovery and Removal time are 0, check if reset signal can be treated as a

synchronous signal and no further optimization is needed.

Hint: check if all blocks receive the reset signal before the next rising edge of the clock for reset

signal, and hence the latter can be treated as synchronous (or not).

Q4. Assuming that there are two extra global interconnects (as shown in Fig. 2 in green) which form a mesh

interconnect path. Estimate the propagation delay from RESET PIN to each receiver module using

Elmore delay method with π lumped RC model.

(Hint: you may refer to the lecture notes for Elmore delay estimation with loops)

Q5. Verify your estimations in Q4. through simulation, and comment on the simulation results.

(*Please show all the calculation steps & relevant screenshots/figures. No marks will be given for

result/value-only answers without any explanation/step.)

Experience 2: Designing simple standard cells & digital circuit, and cleaning up DRC & LVS.

In this lab experience, you are required to design simple standard cells (INV, NAND2/NOR2) using standard

cell method (refer to lecture notes) in 45nm while adhering to the design requirements showing in Table B,

then assemble your own standard cells into a ring oscillator (RO), which is a simple & widely used digital

circuit for periodic signal (e.g., clock) generation, or as process monitors to judge if a particular chip is faster

or slower than nominal expectation.

(x in Table B/C is the second last character of the matriculation # of the first student in group as per Canvas)

Table B: design requirements for your standard cells

cells

INV (all)

NAND2 (for x<=4)

NOR2 (for x>=5)

*standard cell height 10T (for x<=4)

12T (for x>=5)

standard cell width minimize the cell width while meeting design rules and other constraints

top metal layer metal 1 (M1)

pn ratio 1.4

channel length minimum length

finger width maximize the finger width while meeting design rules and other constraints

number of fingers 8 (for x<=4)

4 (for x>=5)

pin position M1

VDD/VSS rails yes (each individual cell should have the rails)

*represent in terms of number of metal tracks (1T = 1 M1 pitch = 1 min. M1 width + 1 min. M1 space)

Table C: number of inverters in your ring oscillator

x y (# of INV cells)

0, 2 , 7 8

1, 3 , 6, 9 10

4 , 5, 8 12

y INV cells

... NAND2/

NOR2

CLKout

your INV cells

your NAND2/NOR2 cells

enable signal

active-high for NAND2

active-low for NOR2

Fig. 3 schematics of a simple ring oscillator

Q1. Show schematics & layout(a) of your INV cell, and the corresponding DRC/LVS results(b)

.

Q2. Show schematics & layout(a) of your NAND2/NOR2 cell, and the corresponding DRC/LVS results(b)

.

Q3. Compose the schematics of your RO based on Table C & Fig. 3. Simulate the behavior of your RO by

feeding a rising/falling edge to the NAND2/NOR2 gate.

Q4. Show the layout & the DRC/LVS results(b) for your RO. (You may use metal 1-3 to connect the pins.)

Q5. Report the frequency, rising time, and falling time of the generated clock (CLKout in Fig.4) from your RO.

Analyze the factors that may affect the three values.

(Hint: this is a pre-layout simulation without layout parasitic, you will explore more in Experience 4.)

(a)Screenshots that clearly show the transistor sizing in schematics, and measurements of cell height &

width in layout via rulers. (b)You will need to add taps for LVS.

Experience 3: Characterizing technology parameters in 45nm using your own cells

In this lab experience, you are going to characterize the pn ratio, FO4, and intrinsic delay (??) for your own

cells using the following circuit template (replace the inverters with the required cells in each question):

Fig. 4: Circuit template to be used

Table D: cells for Q5.

x cell

0, 2, 4, 6, 8 NAND4

1, 3, 5, 7, 9 NOR4

Table E: sizing method for Q5.

x method

0, 2, 4, 6, 8 high speed method

1, 3, 5, 7, 9 standard cell method

Q1. Set M=64. Plot pn ratio (Wp/Wn, from 1 to 2 in 0.2 step) vs rising/falling delay ratio at 1V. You may set

Wn to a fixed value (e.g., from Experience.2.Q1.) and change Wp at each step.

(Hint: You may use tool’s built-in calculator to measure accurate delay).

Q2. Set M=64. Plot pn ratio (Wp/Wn, from 1 to 2 in 0.2 step) vs rising/falling delay ratio at 0.5V. You may set

Wn to a fixed value (e.g., from Experience.2.Q1.) and change Wp at each step.

(Hint: You may use tool’s built-in calculator to measure accurate delay).

Q3. Determine the proper value for M. Plot the simulated FO4 delay vs supply VDD (from 0.5V to 1.1V in

0.05V step) using your INV cell in Experience.2. Assume the maximum logic depth of your digital

integrated circuit is 50·FO4, what is the theoretical maximum operating frequency (ignore setup/hold,

uncertainty, and other variations) at 0.9V?

Q4. Plot the measured propagation delay (??????) vs M (from 16 to 160 in 16 step), find the intrinsic delay ??

using your INV cell in Experience.2. What is the meaning of “M” in this question?

Q5. Build a NAND4/NOR4 gate (refer to Table D.) Fill up below table using your INV cell as the template

inverter, sizing method in Table E, and technology parameters in Q4. Comment on the results and

clearly show all the steps & calculations.

Gate Input theoretical

logical effort

rising

logical

effort (gu)

falling

logical

effort (gu)

average

logical

effort (g)

rising

parasitic

delay (pu)

falling

parasitic

delay (pd)

average

parasitic

delay (p)

A

B

C

D

Experience 4: Post-layout simulation

In this lab experience, you will explore the layout-induced performance downgrade.

(Hint: you may refer to “Cadence IC Design Manual revised” for post-layout simulation)

Q1. Redo Experience 2. Q5. with layout extractions. Comment on your observations.

Q2. Redo Experience 3. Q3. with layout extractions. Comment on your observations.

Survey: individual contribution

Clearly state the contribution (%) from each group member with below template:

Matriculation number (e.g., Axxxxxxxx) Contribution (%)

Report:

Submit your assignment in the form of a report.

Do not report the result directly. Try to explain your results and the steps followed.

Clearly state any additional assumptions that you have taken.

The final report should be in the pdf format only.

Clearly indicate the contribution (in %) of each student on the front page of the report. Intrateam marks may vary based on the contribution reported.

Submission Instructions:

Name your file as: Matric_Number_Assignment_1.pdf

o Ex. A1234567A_Assignment_1.pdf

Upload to Canvas EE5518 ‐> Files ‐> Assignment 1 before 16th October’23 11:59AM.

A penalty of 25% applies for late submissions of up to 1 week. After that, the submissions will not

be considered.

Plagiarism is penalized with a 100% penalty for all SOURCES and RECIPIENTS and will be

reported for further action.