TCSS 372代做、代写Python，Java编程语言、代做C/C++设计

日期：2020-01-19 10:47

TCSS 372 Winter 2020 HW1 Due: By midnight, Friday Jan. 17

(or with 10% late penalty, by midnight Saturday Jan. 18)

Include your last name in your file names. You should turn in a zip file called SMITH.zip which contains

MULT_SMITH.circ and DIV_SMITH.circ. (but use your own name instead of SMITH!)

1. Use Logisim to implement the simple multiplication circuit shown in Figure 3.3 but instead of

multiplying two 32 bits numbers to produce a 64 bit result, your circuit should multiply two 16

bits numbers to produce a 32 bit result.

You must clearly label the product, multiplicand, and multiplier registers. The multiplier register

should hold 16 bits and the other two should hold 32bits . To test your circuit, manually put a

multiplicand of at most 16 bits in the lower half of the 32 bit multiplicand register, put a value in

the multiplier register and set the product register to 0. Your circuit does not have to stop.

After all 1 bits disappear from the multiplier, the product register will no longer change and

should contain the correct result.

The algorithm repeats two steps, addition and shifting. Keep these steps separate by using the

clock to increment a 1 bit counter register. The counter register will have values 0,1,0,1,0,1

etc. as the clock ticks. Use the 0 to trigger the addition and the 1 to trigger the shifting.

Of course, you may not use the Logisim multiplier component.

2. A starting circuit is provided for this problem. Use Logisim to complete the starting circuit so

that it implements the simple division algorithm specified in Figures 3.8 and 3.9. The starting

circuit has labeled registers for the quotient, remainder, and divisor. The circuit also has a

register on the left side which is like a program counter. That register increases by one on each

clock cycle. The ROM is designed to output the values 001, 010, 100 exactly 17 times. You

must use these signals to trigger the three different stages of the division algorithm:

State 001: subtract the divisor from the remainder

State 010: if needed, add the divisor back into the remainder

and add a 1 or 0 bit to the right end of quotient

State 100: shift the divisor right by one bit

Notice that the PC-like register updates on the first half of the clock cycle, but all the other

registers update on the second half of the cycle. YOU MAY NOT CHANGE THIS!

YOU MAY NOT ALTER OR REMOVE THE COMPONENTS OF THE STARTING CIRCUIT. YOU MUST

USE THEM AS IS TO COMPLETE THE DIVIDER!

Naturally, you may not use the divider component provided by Logisim.

Strategy and hints:

The simplest parts are subtracting the divisor from the remainder and shifting the divisor. Try

them first. When you shift the quotient left, you will need to add either a 0 or 1 to the right

end. This choice will be based on whether the remainder is negative or not. A mux will be

useful.

Finding out whether the remainder is negative is a key step. The easiest way to do this is to use

a Splitter. Once you have split the remainder into 32 bits, you can examine the high end bit to

see if it is negative or not.

When you're working with Logisim, you should be sure that the option "Add noise to component

delays" is turned off (no check mark). You can find it by going to the Project menu and choosing

"Options". It will probably stay unchecked once you set it, but you may want to have a second look if

your circuit behaves oddly.

If you find a component acting strangely, check that you haven't accidentally connected a couple ports

together.